25-03-2021

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  1. Drivers Quizzes
  2. Drivers Circle

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Drivers

Author: Robert Jarzmik <robert.jarzmik@free.fr>

24.1. Constraints¶

  1. Image size for YUV422P formatAll YUV422P images are enforced to have width x height % 16 = 0.This is due to DMA constraints, which transfers only planes of 8 bytemultiples.

24.2. Global video workflow¶

  1. QCI stoppedInitialy, the QCI interface is stopped.When a buffer is queued (pxa_videobuf_ops->buf_queue), the QCI starts.

  2. QCI startedMore buffers can be queued while the QCI is started without halting thecapture. The new buffers are “appended” at the tail of the DMA chain, andsmoothly captured one frame after the other.

    Once a buffer is filled in the QCI interface, it is marked as “DONE” andremoved from the active buffers list. It can be then requeud or dequeued byuserland application.

    Once the last buffer is filled in, the QCI interface stops.

  3. Capture global finite state machine schema

Drivers Quizzes

24.3. DMA usage¶

  1. DMA flow
    • first buffer queued for captureOnce a first buffer is queued for capture, the QCI is started, but datatransfer is not started. On “End Of Frame” interrupt, the irq handlerstarts the DMA chain.
    • capture of one videobufferThe DMA chain starts transferring data into videobuffer RAM pages.When all pages are transferred, the DMA irq is raised on “ENDINTR” status
    • finishing one videobufferThe DMA irq handler marks the videobuffer as “done”, and removes it fromthe active running queueMeanwhile, the next videobuffer (if there is one), is transferred by DMA
    • finishing the last videobufferOn the DMA irq of the last videobuffer, the QCI is stopped.
  2. DMA prepared buffer will have this structure

This structure is pointed by dma->sg_cpu.The descriptors are used as follows:

  • desc-sg[i]: i-th descriptor, transferring the i-th sgelement to the video buffer scatter gather
  • finisher: has ddadr=DADDR_STOP, dcmd=ENDIRQEN
  • linker: has ddadr= desc-sg[0] of next video buffer, dcmd=0

For the next schema, let’s assume d0=desc-sg[0] .. dN=desc-sg[N],“f” stands for finisher and “l” for linker.A typical running chain is :

After the chaining is finished, the chain looks like :

Drivers Circle

  1. DMA hot chaining timeslice issue

As DMA chaining is done while DMA _is_ running, the linking may be donewhile the DMA jumps from one Videobuffer to another. On the schema, thatwould be a problem if the following sequence is encountered :

  • DMA chain is Videobuffer1 + Videobuffer2
  • pxa_videobuf_queue() is called to queue Videobuffer3
  • DMA controller finishes Videobuffer2, and DMA stops
  • pxa_dma_add_tail_buf() is called, the Videobuffer2 “finisher” isreplaced by a “linker” to Videobuffer3 (creation of new_link)
  • pxa_videobuf_queue() finishes
  • the DMA irq handler is called, which terminates Videobuffer2
  • Videobuffer3 capture is not scheduled on DMA chain (as it stopped !!!)
  • pxa_camera_check_link_miss() is calledThis checks if the DMA is finished and a buffer is still on thepcdev->capture list. If that’s the case, the capture will be restarted,and Videobuffer3 is scheduled on DMA chain.
  • the DMA irq handler finishes

Note

If DMA stops just after pxa_camera_check_link_miss() reads DDADR()value, we have the guarantee that the DMA irq handler will be called backwhen the DMA will finish the buffer, and pxa_camera_check_link_miss() willbe called again, to reschedule Videobuffer3.

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